PIC18F45J11-I/ML【PDF 9/228 页】IC PIC MCU FLASH 32K 2V 44-QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3862

5页 6页 7页 8页 [9页]10页 11页 12页 13页

dsPIC30F3014/4013

DS70138G-page 106

2010 Microchip Technology Inc.

16.3.4

TRANSMIT INTERRUPT

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.

The transmitter generates an edge to set the UxTXIF

bit. The condition for generating the interrupt depends

on the UTXISEL control bit:

If UTXISEL = 0, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR). This means

that the transmit buffer has at least one empty

word.

If UTXISEL = 1, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR) and the

transmit buffer is empty.

Switching between the two Interrupt modes during

operation is possible and sometimes offers more

flexibility.

16.3.5

TRANSMIT BREAK

Setting the UTXBRK bit (UxSTA<11>) causes the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

To send a Break character, the UTXBRK bit must be set

by software and must remain set for a minimum of

13 baud clock cycles. The UTXBRK bit is then cleared

by software to generate Stop bits. The user must wait

for a duration of at least one or two baud clock cycles

in order to ensure a valid Stop bit(s) before reloading

the UxTXB, or starting other transmitter activity. Trans-

mission of a Break character does not generate a

transmit interrupt.

16.4

Receiving Data

16.4.1

RECEIVING IN 8-BIT OR 9-BIT

DATA MODE

The following steps must be performed while receiving

8-bit or 9-bit data:

Set

the

UART

(see

Section 16.3.1

“Transmitting in 8-Bit Data Mode”).

Enable

the

UART

(see

Section 16.3.1

“Transmitting in 8-Bit Data Mode”).

A receive interrupt is generated when one or

more data words have been received, depend-

ing on the receive interrupt settings specified by

the URXISEL bits (UxSTA<7:6>).

Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

Read the received data from UxRXREG. The act

of reading UxRXREG moves the next word to

the top of the receive FIFO, and the PERR and

FERR values are updated.

16.4.2

RECEIVE BUFFER (UXRXB)

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0 means that the

buffer is empty. If a user attempts to read an empty buf-

fer, the old values in the buffer are read and no data

shift occurs within the FIFO.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

power-saving mode.

16.4.3

RECEIVE INTERRUPT

The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register. The

interrupt flag is set by an edge generated by the

receiver. The condition for setting the receive interrupt

flag depends on the settings specified by the

URXISEL<1:0> (UxSTA<7:6>) control bits.

If URXISEL<1:0> = 00 or 01, an interrupt is gen-

erated every time a data word is transferred

from the Receive Shift register (UxRSR) to the

receive buffer. There may be one or more

characters in the receive buffer.

If URXISEL<1:0> = 10, an interrupt is generated

when a word is transferred from the Receive Shift

result of the transfer, contains 3 characters.

If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift

a result of the transfer, contains 4 characters

(i.e., becomes full).

Switching between the Interrupt modes during opera-

tion is possible, though generally not advisable during

normal operation.

16.5

Reception Error Handling

16.5.1

RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:

The receive buffer is full.

The Receive Shift register is full, but unable to

transfer the character to the receive buffer.

The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

Once OERR is set, no further data is shifted in UxRSR

(until the OERR bit is cleared in software or a Reset

occurs). The data held in UxRSR and UxRXREG

remains valid.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式